Video decoders vary broadly in processing power, speed, storage capacity, and video quality. For example, a decoder may have lower processing power capabilities with just enough to decode an average video sequence of acceptable quality. Whereas, a decoder with higher processing power capabilities is likely to have little trouble providing a video sequence of acceptable quality, but has excess unused power.
One way to regulate the various decoders is to provide different decoding processes for the different decoders. However, the impracticality of maintaining different decoding processes is prohibitively expensive and labor-intensive. Therefore, a standard decoding process that is scalable to regulate various decoders' capabilities is preferred.
Such a scalable decoding process should efficiently allocate power to produce acceptable video quality for both lower and higher power decoders. In higher power decoders, the efficiently allocated decoding process may result in additional power for other functions of the decoder.
Conventional processes for decoder power allocation react to the decoding timeliness of the sequence, rather than to the power capabilities of the decoder itself. That is, the processes adjust only when it is highly likely that display of a decoded sequence will be delayed. However, the adjustments often take effect too slowly or demand too much power too quickly, which is problematic for any decoder, particularly lower power decoders.
Accordingly, there is a need in the art for a way to regulate decode-side processing for various video decoders having various power capabilities.